The present invention relates to semiconductor devices and, more specifically, to a termination structure for semiconductor devices, such as MOS gate controlled ("MOS-gated") semiconductor devices.
MOS-gated devices are well known in the art and include devices such as the MOS-gated devices shown in U.S. patent application Ser. No. 08/299,533, filed Sep. 1, 1994 (IR-1113), the subject matter of which is incorporated herein by reference. MOS-gated devices also include power MOSFETS, MOS-gated thyristors, gate turn-off devices and the like.
The MOS-gated devices are typically formed of a plurality of active cells which include cells located at the periphery of the die. The peripheral cells, when subject to the full source-to-drain voltage, are prone to avalanche breakdown between the outermost portion of the cell and the adjacent street.
It is therefore necessary to provide a device structure that prevents breakdown at the active peripheries of the chip.
The manufacturing process for devices that include such structures includes a number of photolithographic masking steps and critical mask alignment steps each of which adds manufacturing time and expense as well as provides possible sources of device defects.
It is therefore also desirable to employ a termination structure that occupies a minimum surface area of the chip and does not require added masking steps.